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PIC18F2331/2431/4331/4431

DS39616D-page 48

2010 Microchip Technology Inc.

5.1

RCON Register

Device Reset events are tracked through the RCON

indicate that a specific Reset event has occurred. In most

cases, these bits can only be cleared by the event and

must be set by the application after the event. The state

of these flag bits, taken together, can be read to indicate

the type of Reset that just occurred. This is described in

more detail in Section 5.6 “Reset State of Registers”.

The RCON register also has control bits for setting

interrupt priority (IPEN) and software control of the

BOR (SBOREN). Interrupt priority is discussed in

Section 10.0

“Interrupts”

. BOR is covered in

Section 5.4 “Brown-out Reset (BOR)”

Note 1:

If the BOREN Configuration bit is set

(Brown-out Reset enabled), the BOR bit

is ‘1’ on a Power-on Reset. After a

Brown-out Reset has occurred, the BOR

bit will be cleared and must be set by

firmware to indicate the occurrence of the

next Brown-out Reset.

It is recommended that the POR bit be

set after a Power-on Reset has been

detected, so that subsequent Power-on

Resets may be detected.

REGISTER 5-1:

RCON: RESET CONTROL REGISTER

R/W-0

U-0

R/W-1

R-1

R/W-0

IPEN

—

—RI

POR(2)

BOR(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

IPEN:

Interrupt Priority Enable bit

= Enable priority levels on interrupts

= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6-5

Unimplemented:

Read as ‘0’

bit 4

RI: RESET

Instruction Flag bit

= The RESET instruction was not executed (set by firmware only)

= The RESET instruction was executed causing a device Reset (must be set in software after a

Brown-out Reset occurs)

bit 3

TO:

Watchdog Time-out Flag bit

= Set by power-up, CLRWDT instruction or SLEEP instruction

= A WDT time-out occurred

bit 2

PD:

Power-Down Detection Flag bit

= Set by power-up or by the CLRWDT instruction

= Set by execution of the SLEEP instruction

bit 1

POR:

Power-on Reset Status bit(2)

= A Power-on Reset has not occurred (set by firmware only)

= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR:

Brown-out Reset Status bit(1)

= A Brown-out Reset has not occurred (set by firmware only)

= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1:

If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

The actual Reset value of POR is determined by the type of device Reset. See the notes following this

register and Section 5.6 “Reset State of Registers” for additional information.

Note 1:

It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent

Power-on Resets may be detected.

Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to

‘1’ by software immediately after a Power-on Reset).

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